e

E1

D1

b

SE

SD

0.05 M

S

AB

B

A

E

D

Pin 1

Ind ic a tor

Ma rking

see Note 7

A3

A2

A

A1

0.05 S

S

FRONTVIEW

TOP VIEW

BOTTOM VIEW

A

1

0.50

0.17

0.30

0.040

0.23

0.35

0.70

0.35

0.175

0.00

A

AAAA

SIDE VIEW

0.727

1.077

1

B

3

2

TITLE

DOCUMENTCONTROL NO.

REV.

1

1

APPROVAL

COMMON DIMENSIONS

A

A2

A1

A3

b

E1

D1

e

SD

SE

MAX

0.03

0.03

BASIC

REF

BASIC

NOTES:

1. Termina l p itc h is d efined b y termina l c enter to c enter va lue.

2. Outer d imension is d efined b y c enter lines b etween sc rib e lines.

3. All d imensions in millimeter.

4. Ma rking shown is for p a c ka g e orienta tion referenc e only.

5. Tolera nc e is ± 0.02 unless sp ec ified otherwise.

6. All d imensions a p p ly to Pb Free (+) p a c ka g e c od es only.

7. Front - sid e finish c a n b e either Bla c k or Clea r.

BASIC

BASIC

- DRAWING NOTTO SCALE -

C

BASIC

BASIC

maxim

integrated TM

21-100086

PACKAGE OUTLINE 6 BUMPS

THIN WLP PKG. 0.35 mm PITCH,

N60D1+1

D

0.025

0.025

E

DEPOPULATED BUMPS:

NONE

6 SOT23

Package Code

U6+1

Outline Number

21-0058

Land Pattern Number

90-0175

THERMAL RESISTANCE, FOUR-LAYER BOARD

Junction to Ambient (θJA)

230°C/W

Junction to Case (θJC)

76°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.

Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different

suffix character, but the drawing pertains to the package regardless of RoHS status.

Note:

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a

four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/

thermal-tutorial.

MAX40000/MAX40001

1.7V, nanoPower Comparators with Built-In

Reference

www.maximintegrated.com

Maxim Integrated | 6