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TPS37-Q1 Datasheet(PDF) 32 Page - Texas Instruments |
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TPS37-Q1 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 47 page ![]() • Do not have high voltage metal pads or traces closer than 20 mils (0.5 mm) to the low voltage metal pads or traces. 10.5.2 Layout Example The DSK layout example in Figure 10-5 shows how the TPS37-Q1 is laid out on a printed circuit board (PCB) with user-defined delays. Monitored Voltage Overvoltage Flag CVDD 2 9 3 8 7 5 6 10 GND RPU2 1 VDD RPU1 Undervoltage Flag TPS37-Q1 Monitored Voltage V PULL-UP V PULL-UP 4 GND Vias used to connect pins for application-specific connections CSENSE1 CSENSE2 DSK Package Figure 10-5. TPS37-Q1 DSK Package Recommended Layout TPS37-Q1 SNVSBD9E – AUGUST 2020 – REVISED AUGUST 2023 www.ti.com 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS37-Q1 |
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