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DAC39RF10 Datasheet(PDF) 141 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 141 Page - Texas Instruments |
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141 / 232 page  Table 8-3. DEVICE_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 MODE R/W 0h 0 : Normal operation (default) 1 : Reserved 2 : Reserved 3 : Full power down. The user should follow the recommendations in Section 9.1.6 in this mode to avoid reliability concerns. 8.3 CHIP_TYPE Register (Offset = 3h) [reset = 04h] CHIP_TYPE is shown in Figure 8-3 and described in Table 8-4. Return to the Register Summary Table. Chip Type (read-only: 0x04) Figure 8-3. CHIP_TYPE Register 7 6 5 4 3 2 1 0 RESERVED CHIP_TYPE R/W-0h R-4h Table 8-4. CHIP_TYPE Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 CHIP_TYPE R 4h Always returns 0x4, indicating that the part is a high speed DAC. 8.4 CHIP_ID Register (Offset = 4h) [reset = 003Bh] CHIP_ID is shown in Figure 8-4 and described in Table 8-5. Return to the Register Summary Table. Chip Identification (read-only) Figure 8-4. CHIP_ID Register 15 14 13 12 11 10 9 8 CHIP_ID R-0h 7 6 5 4 3 2 1 0 CHIP_ID R-3Bh Table 8-5. CHIP_ID Register Field Descriptions Bit Field Type Reset Description 15-0 CHIP_ID R 003Bh Always returns 0x003B indicating it is the DAC39RF10 device family 8.5 CHIP_VERSION Register (Offset = 6h) [reset = 02h] CHIP_VERSION is shown in Figure 8-5 and described in Table 8-6. Return to the Register Summary Table. Chip Version (read-only) www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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