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DAC39RF10 Datasheet(PDF) 144 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 144 Page - Texas Instruments |
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144 / 232 page  Table 8-10. SYSREF_ALIGN Register Field Descriptions (continued) Bit Field Type Reset Description 0 SYSREF_ALIGN_EN R/W 0b When this bit is set, the chip realigns to each detected SYSREF edge. This affects both the external clock divider and the JESD subsystem. SYSREF_TERM Register (Offset = 00A1h) [reset = 00h] SYSREF_TERM is shown in Figure 8-10 and described in Table 8-11. Return to the Register Summary Table. SYSREF Termination Configruation Figure 8-10. SYSREF_TERM Register 7 6 5 4 3 2 1 0 RESERVED SYSREF_RECV_LVPECL R/W-00h R/W-0b Table 8-11. SYSREF_TERM Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h Reserved 0 SYSREF_RECV_LVPECL R/W 0b 0: SYSREF termination is 100 Ohm differential with Vcm of 0.4V 1: SYSREF termination is singled ended 50 Ohm to GND (LVPECL mode) 8.10 JESD_EN Register (Offset = 0100h) [reset = 00h] JESD_EN is shown in Figure 8-11 and described in Table 8-12. Return to the Register Summary Table. JESD204C Subsystem Enable Figure 8-11. JESD_EN Register 7 6 5 4 3 2 1 0 RESERVED JESD_EN R/W-00h R/W-0b Table 8-12. JESD_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 JESD_EN R/W 0b 0 : Disable JESD204C interface 1 : Enable JESD204C interface When JESD_EN=0, the JESD204C subsystem is held in reset and the SERDES PHY is disabled. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC. Note: This register should only be changed when DP_EN=0. 8.11 JMODE Register (Offset = 0101h) [reset = 00h] JMODE is shown in Figure 8-12 and described in Table 8-13. Return to the Register Summary Table. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 144 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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