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DAC39RF10 Datasheet(PDF) 146 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 146 Page - Texas Instruments |
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146 / 232 page  Figure 8-14. JCTRL Register (continued) RESERVED TI_MODE SUBCLASS JENC RESERVED SFORMAT SCR R/W-0b R/W-0b R/W-0b R/W-0b R/W-00b R/W-1b R/W-1b Table 8-15. JCTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0b 6 TI_MODE R/W 0b 0 : JESD204C standard mode (default) 1 : TI Mode - set this when using TI FPGA transmitter IP 5 SUBCLASS R/W 0b Specify how the elastic buffer is released: 0 : Subclass 0 operation (default). Release the elastic buffer immediately once all lanes have starting writing to the buffer. 1 : Subclass 1 operation. Release the elastic buffer on a release opportunity defined by the LMFC/LEMC and RBD. 4 JENC R/W 0b 0 : Use 8b/10b link layer 1 : Use 64b/66b link layer 3-2 RESERVED R/W 0b 1 SFORMAT R/W 1b Input sample format for JESD204C samples 0 : Offset binary 1 : Signed 2’s complement (default) 0 SCR R/W 1b 0 : 8b/10b Scrambler disabled 1 : 8b/10b Scrambler enabled (default) The 8b/10b scrambler is recommended to improve spurious noise and make sure that certain sample payloads cannot prevent the JESD204C receiver from detecting incorrect code-group or lane alignment. This register has no effect on 64b/66b modes (which are always scrambled). 8.14 SHMODE Register (Offset = 0104h) [reset = 00h] SHMODE is shown in Figure 8-15 and described in Table 8-16. Return to the Register Summary Table. JESD204C Sync Word Mode Figure 8-15. SHMODE Register 7 6 5 4 3 2 1 0 RESERVED SHMODE R/W-0b R/W-00b Table 8-16. SHMODE Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 00h DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 146 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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