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DAC39RF10 Datasheet(PDF) 142 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 142 Page - Texas Instruments |
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142 / 232 page ![]() Figure 8-5. CHIP_VERSION Register 7 6 5 4 3 2 1 0 CHIP_VERSION R-2h Table 8-6. CHIP_VERSION Register Field Descriptions Bit Field Type Reset Description 7-0 CHIP_VERSION R 02h 1: PG1.0 2: PG2.0 8.6 VENDOR_ID Register (Offset = Ch) [reset = 0451h] VENDOR_ID is shown in Figure 8-6 and described in Table 8-7. Return to the Register Summary Table. Vendor Identification (default: 0x0451) Figure 8-6. VENDOR_ID Register 15 14 13 12 11 10 9 8 VENDOR_ID R-04h 7 6 5 4 3 2 1 0 VENDOR_ID R-51h Table 8-7. VENDOR_ID Register Field Descriptions Bit Field Type Reset Description 15-0 VENDOR_ID R 451h TI vendor ID 8.7 SYSREF_CTRL Register (Offset = 0080h) [reset = 40h] SYSREF_CTRL is shown in Figure 8-7 and described in Table 8-8. Return to the Register Summary Table. SYSREF Control Figure 8-7. SYSREF_CTRL Register 7 6 5 4 3 2 1 0 SYSREF_PRO C_EN SYSREF_REC V_SLEEP SYSREF_PS_E N SYSREF_ZOO M SYSREF_SEL R/W-0b R/W-1b R/W-0b R/W-0b R/W-0h Table 8-8. SYSREF_CTRL Register Field Descriptions Bit Field Type Reset Description 7 SYSREF_PROC_EN R/W 0h When set, this bit enables the SYSREF processor. When this is enabled, the system receives and processes each new SYSREF edge. User should always clear SYSREF_RECV_SLEEP before setting this bit. This bit is provided to allow the SYSREF receiver to stabilize before allowing the SYSREF to come to the digital. 6 SYSREF_RECV_SLEEP R/W 1b Clear this bit to enable the SYSREF receiver circuit. User should always clear SYSREF_PROC_EN before setting this bit. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 142 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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