Electronic Components Datasheet Search
  English  ▼

X  

DAC39RF10 Datasheet(PDF) 150 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC39RF10 Datasheet(HTML) 150 Page - Texas Instruments

Back Button DAC39RF10 Datasheet HTML 146Page - Texas Instruments DAC39RF10 Datasheet HTML 147Page - Texas Instruments DAC39RF10 Datasheet HTML 148Page - Texas Instruments DAC39RF10 Datasheet HTML 149Page - Texas Instruments DAC39RF10 Datasheet HTML 150Page - Texas Instruments DAC39RF10 Datasheet HTML 151Page - Texas Instruments DAC39RF10 Datasheet HTML 152Page - Texas Instruments DAC39RF10 Datasheet HTML 153Page - Texas Instruments DAC39RF10 Datasheet HTML 154Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 150 / 232 page
background image
Table 8-22. RATE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
RATE
R/W
00b
Controls the frequency multiplier from the PHY PLL to the serial line
rate. See PLL Control. Affects all lanes.
RATE: Multiplier
00b: 4
01b: 2
10b: 1
11b: 0.5
Note: This register should only be changed when JESD_EN=0.
8.21 LB_VRANGE Register (Offset = 010Bh) [reset = 00h]
LB_VRANGE is shown in Figure 8-22 and described in Table 8-23.
Return to the Register Summary Table.
JESD204C PLL VCO Range. Note: This register should only be changed when JESD_EN=0.
Figure 8-22. LB_VRANGE Register
7
6
5
4
3
2
1
0
RESERVED
VRANGE
R/W-0h
R/W-0b
Table 8-23. LB_VRANGE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
00h
0
VRANGE
R/W
0b
This bit must be set if the PLL/VCO frequency is below 2.17GHz.
See PLL Control.
8.22 JSYNC_N Register (Offset = 0120h) [reset = 01h]
JSYNC_N is shown in Figure 8-7 and described in Table 8-8.
Return to the Register Summary Table.
JESD204C Manual Sync Request
Figure 8-23. JSYNC_N Register
7
6
5
4
3
2
1
0
RESERVED
JSYNC_N
R/W-00h
R/W1C
Table 8-24. JSYNC_N Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
00h
0
JSYNC_N
R/W
1b
Set this bit to 0 to manually assert the SYNC signal. For normal
operation, leave this bit set to 1.
Note: Behavior of JSYNC_N=0 is undefined when JENC=1.
8.23 JTEST Register (Offset = 0121h) [reset = 00h]
JTEST is shown in Figure 8-24 and described in Table 8-25.
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
www.ti.com
150
Submit Document Feedback
Copyright © 2026 Texas Instruments Incorporated
Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com