DAC39RF10 datasheet(147/232 Pages) TI2

147 / 232 page

Table 8-16. SHMODE Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

SHMODE

R/W

00b

Select the mode for the 64b/66b sync word (32 bits of data per

multi-block). This only applies when JENC=1 (64b/66b mode).

0 : Enable CRC-12 checking (JESD204C Table 41) (default setting)

1 : RESERVED

2 : RESERVED

3 : RESERVED

Note: This device does not support any JESD204C command

features. All command fields are ignored by the receiver.

Note: This register should only be changed when JESD_EN=0.

8.15 KM1 Register (Offset = 0105h) [reset = 1Fh]

KM1 is shown in Figure 8-16 and described in Table 8-17.

Return to the Register Summary Table.

JESD204C K Parameter (minus 1)

Figure 8-16. KM1 Register

KM1

R/W-1Fh

Table 8-17. KM1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

KM1

R/W

1Fh

K is the number of frames per multiframe, and K-1 shall be

programmed here when using the 8b/10b link layer (see JENC).

Depending on the JMODE setting, there are constraints on the legal

values of K (see Table 7-22 and KR). Programming an illegal value

for K will cause the link to malfunction.

The default value is KM1=31, which corresponds to K=32.

Note: For modes using the 64b/66b link layer, the KM1 register is

ignored. The effective value of K is 256*E/F.

Note: This register should only be changed when JESD_EN=0.

8.16 RBD Register (Offset = 106h) [reset = 00h]

RBD is shown in Figure 8-17 and described in Table 8-18.

Return to the Register Summary Table.

JESD204C Release Buffer Delay

Figure 8-17. RBD Register

RESERVED

RBD

R/W-0b

R/W-000000b

Table 8-18. RBD Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

00b

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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