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DAC39RF10 Datasheet(PDF) 148 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 148 Page - Texas Instruments |
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148 / 232 page  Table 8-18. RBD Register Field Descriptions (continued) Bit Field Type Reset Description 5-0 RBD R/W 000000b This register shifts the elastic buffer release opportunities. Increasing RBD by 1 delays the release opportunities by 4 bytes (octets). The legal RBD range is 0 to K*F/4-1. For 64b/66b modes, the legal RBD range is 0 to 63. See Programming RBD. Note: This register should only be changed when JESD_EN=0. 8.17 JESD_STATUS Register (Offset = 0107h) [reset = NA] JESD_STATUS is shown in Figure 8-18 and described in Table 8-19. Return to the Register Summary Table. JESD204C / System Status Figure 8-18. JESD_STATUS Register 7 6 5 4 3 2 1 0 EB_ERR LINK_UP JSYNC_STATE REALIGNED ALIGNED PLL_LOCKED RESERVED R/W1C R R R/W1C R R R Table 8-19. JESD_STATUS Register Field Descriptions Bit Field Type Reset Description 7 EB_ERR R/W1C NA Elastic buffer experienced underflow/overflow. Check RBD. Write a 1 to clear this bit. 6 LINK_UP R NA When set, indicates that the JESD204C link is up (elastic buffer released). 5 JSYNC_STATE R NA Returns the state of the JESD204C SYNC signal. 0 : SYNC asserted 1 : SYNC de-asserted 4 REALIGNED R/W1C NA When any clock dividers or the LMFC/LEMC counters are realigned by SYSREF, this bit gets set. Write a 1 to clear this bit. The behavior of this bit is undefined when SUBCLASS=0. 3 ALIGNED R NA When set, indicates that the last SYSREF pulse was consistent with the SYSREF-associated clock dividers (including the LMFC/LEMC). This bit is read-only (cannot be cleared via SPI). After JESD_EN is set, the part may require up to 7 SYSREF pulses to achieve full alignment and set this bit. The behavior of this bit is undefined when SUBCLASS=0. 2 PLL_LOCKED R NA When high, indicates that all enabled SerDes PLLs are locked. 1-0 RESERVED R NA 8.18 REFDIV Register (Offset = 0108h) [reset = 30h] REFDIV is shown in Figure 8-19 and described in Table 8-20. Return to the Register Summary Table. JESD204C Reference Divider Figure 8-19. REFDIV Register 7 6 5 4 3 2 1 0 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 148 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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