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DAC39RF10 Datasheet(PDF) 149 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 149 Page - Texas Instruments |
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149 / 232 page  Figure 8-19. REFDIV Register (continued) RESERVED REFDIV R/W-0b R/W-30h Table 8-20. REFDIV Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00b 5-0 REFDIV R/W 30h Specifies the frequency divisor to generate the PHY PLL reference clock (FREF) from the DAC clock (FCLK). See PLL Control. The following values are legal: 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48. All other values are reserved and produce undefined behavior. 8.19 MPY Register (Offset = 0109h) [reset = 14h] MPY is shown in Figure 8-20 and described in Table 8-21. Return to the Register Summary Table. JESD204C PLL Multiplier Figure 8-20. MPY Register 7 6 5 4 3 2 1 0 MPY R/W-14h Table 8-21. MPY Register Field Descriptions Bit Field Type Reset Description 7-0 MPY R/W 14h Specifies the PLL frequency multiplier for the PHY. See PLL Control. The following values are allowed for this design: MPY: Frequency Multiplier 16 (0x10): 4 20 (0x14): 5 33 (0x21): 8.25 40 (0x28): 10 Note: This register should only be changed when JESD_EN=0. 8.20 RATE Register (Offset = 010Ah) [reset = 00h] RATE is shown in Figure 8-21 and described in Table 8-22. Return to the Register Summary Table. JESD204C Receive Rate Figure 8-21. RATE Register 7 6 5 4 3 2 1 0 RESERVED RATE R/W-00h R/W-00b Table 8-22. RATE Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 00h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 149 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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