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DAC39RF10 Datasheet(PDF) 151 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 151 Page - Texas Instruments |
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151 / 232 page  Return to the Register Summary Table. JESD204C Test Control Figure 8-24. JTEST Register 7 6 5 4 3 2 1 0 RESERVED JTEST R/W-000b R/W-00h Table 8-25. JTEST Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 JTEST R/W 0b PRBS Test Modes: 0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS9 test mode 3 : PRBS15 test mode 4 : PRBS31 test mode 5-31: RESERVED When a PRBS test mode is enabled, see BER_EN. Note: This register should only be changed when JESD_EN=0. 8.24 JTIMER Register (Offset = 0124h) [reset = 00h] JTIMER is shown in Figure 8-25 and described in Table 8-26. Return to the Register Summary Table. Note: This register should only be changed when JESD_EN=0. JESD204C Watchdog Timer Figure 8-25. JTIMER Register 7 6 5 4 3 2 1 0 JTPLL RESERVED JTR RESERVED JTT R/W-0b R/W-0b R/W-0b R/W-0b R/W-000b Table 8-26. JTIMER Register Field Descriptions Bit Field Type Reset Description 7 JTPLL R/W 1b When this bit is set, the SerDes PLL is also reset when the watchdog timer expires. When this bit is 0, only the SerDes receiver is reset. 6 RESERVED R/W 0b 5-4 JTR R/W 00b This register determines how much the watchdog counter is decremented when the link is up and CRC_FAULT is not set. JTR : Watchdog Counter Decrement : Approximate Link Uptime % required to prevent the SerDes from being reset 0 : 1 : 99.25% 1 : 2 : 98.46% 2 : 8 : 94.12% 3 : 16 : 88.89% 3 RESERVED R/W 0b www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 151 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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