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DAC39RF10 Datasheet(PDF) 174 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
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DAC39RF10 Datasheet(HTML) 174 Page - Texas Instruments

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Table 8-69. TX_EN_SEL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
USE_TX_EN0
R/W
1b
0: DACA is controlled by the TXEN0 ball. In this mode, TX_EN0
register is ignored.
1: DACA is controlled by the TX_EN0 register. In this mode the
TXEN0 ball input does not affect the transmit enable for DACA.
Note: USE_TX_EN1 and USE_TX_EN0 should be programmed to
the same value (individual channel control is not supported).
8.66 TX_EN Register (Offset = 02F9h) [reset = 03h]
TX_EN is shown in Figure 8-68 and described in Table 8-70.
Return to the Register Summary Table.
Transmitter Enable Control
Figure 8-68. TX_EN Register
7
6
5
4
3
2
1
0
TX_EN1
TX_EN0
R/W-00h
R/W-1b
R/W-1b
Table 8-70. TX_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
00h
1
TX_EN1
R/W
1b
When USE_TX_EN1 = 1, this bit controls the transmit enable for
DACB.
Note: TX_EN1 and TX_EN0 should be programmed to the same
value (individual channel control is not supported).
0
TX_EN0
R/W
1b
When USE_TX_EN0 = 1, this bit controls the transmit enable for
DACA
Note: TX_EN1 and TX_EN0 should be programmed to the same
value (individual channel control is not supported).
8.67 NCO_CTRL Register (Offset = 0300h) [reset = 00h]
NCO_CTRL is shown in Figure 8-69 and described in Table 8-71.
Return to the Register Summary Table. Note: This register should only be changed when DP_EN=0.
NCO Enable
Figure 8-69. NCO_CTRL Register
7
6
5
4
3
2
1
0
FR_EN
RESERVED
NCO_SC
DDS_EN
NCO_EN
R/W-0b
R/W-0h
R/W-0b
R/W-0b
R/W-0b
Table 8-71. NCO_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FR_EN
R/W
0b
When set, the Fast Reconfiguration (FR) interface is enabled and
NCO frequency, phase, dither, and accumulator reset is controlled by
the FR registers rather than the SPI registers.
6-3
RESERVED
R/W
0h
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
www.ti.com
174
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Copyright © 2026 Texas Instruments Incorporated
Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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