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DAC39RF10 Datasheet(PDF) 178 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC39RF10 Datasheet(HTML) 178 Page - Texas Instruments

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Table 8-76. NCO_SS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
NCO_SS
R/W
0b
When this bit is set, all NCOs will continuously self-synchronize
every 256 DAC clock cycles.
In a radiation environment, the user can set NCO_SS to continuously
transfer the upset-immune AMP, FREQ and PHASE register values
to the internal (non-immune) registers inside the NCOs. This is
helpful for generating tones under radiation without the need for an
external, periodic synchronization source (such as SYSREF).
NCO_SS can be changed while the NCOs are operating (DP_EN=1).
To write a new FREQ, AMP, or PHASE value, clear NCO_SS first,
and then set it again after the new values are written. All values go
into effect simultaneously on all NCOs.
The user should make sure that NCO_AR=0 whenever NCO_SS=1
(otherwise the NCO accumulators and/or reference counters keep
getting reset).
If the user also sets NCO_SC=1 and NCO_CONT=0, then all four
NCOs maintain coherency with each other under radiation, but there
may be no coherence with an external component. Each NCO
accumulator is continuously seeded from the reference counter in
DUC/DDS channel 0. This feature can be used to generate coherent
harmonic tones to cancel out harmonic distortion in the DAC.
AMP[3:0] Register (Offset = 0318h) [reset = 0000h]
AMP[3:0] is described in Table 8-77. AMP[0] starts at address 0x0318, AMP[1] at address 0x031A, AMP[2] at
address 0x031C and AMP[3] at address 0x031E.
Return to the Register Summary Table.
Table 8-77. AMP[3:0] Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
AMP[3:0]
R/W
0000h
Specifies the DDS amplitude for DDS channel n. 16-bit signed value.
This register only applies to DDS Operation.
Note: Changes to this register do not take effect until the next sync
event specified by NCO_SYNC_SRC.
Note: This register should only be changed when DP_EN=0 or
updates to the NCOs are scheduled to occur away from the change.
(See NCO_SYNC.)FREQ[0] Register (Offset = 0320h) [reset =
0000000000000000h]
FREQ[0] is described in Table 8-78.
Return to the Register Summary Table.
FREQ for NCO0 Accumulator.
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
www.ti.com
178
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Copyright © 2026 Texas Instruments Incorporated
Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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