DAC39RF10 datasheet(182/232 Pages) TI2

182 / 232 page

Table 8-84. PHASE2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE2

R/W

Phase is added late so this register can be written during operation

to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the

phase accumulator. The phase (in radians) is PHASE2 * 2-16 * 2π.

This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync

event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or

updates to the NCOs are scheduled to occur away from the change.

(See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

8.79 PHASE3 Register (Offset = 0346h) [reset = 0000h]

PHASE3 is described in Table 8-85.

Return to the Register Summary Table.

Phase for NCO3 Accumulator.

Table 8-85. PHASE3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE3

R/W

Phase is added late so this register can be written during operation

to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the

phase accumulator. The phase (in radians) is PHASE3 * 2-16 * 2π.

This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync

event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or

updates to the NCOs are scheduled to occur away from the change.

(See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

AMP_R[3:0] Register (Offset = 0378h) [reset = NA]

AMPR[3:0] is described in Table 8-86. AMP_R[0] starts at addess offset 0x0378, AMP_R[1] at address offset

0x37A, AMP_R[2] at address offset 0x37C and AMP_R[3] at address offset 0x37E

Return to the Register Summary Table.

Table 8-86. AMP_R[3:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

AMP_R[n]

This provides a readback of the amplitude setting that is currently

in use by the DDS channel n. Format is 16-bit signed. This register

is only applicable when DDS_EN=1. When DDS_EN=0, the return

value is undefined. The value is sampled as each byte is read,

so it may return incoherent data if the amplitude changes during

readback.

8.80 FREQ_R0 Register (Offset = 0380h) [reset = NA, read-only]

FREQ_R0 is described in Table 8-87.

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

182

Submit Document Feedback

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

DAC39RF10 Datasheet(PDF) 182 Page - Texas Instruments

DAC39RF10 Datasheet(HTML) 182 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL