 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DAC39RF10 Datasheet(PDF) 186 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DAC39RF10 Datasheet(HTML) 186 Page - Texas Instruments |
|
|
186 / 232 page  Table 8-97. TS_TEMP Register Field Descriptions Bit Field Type Reset Description 7-0 TS_TEMP R NA Returns the temperature sensor reading. This returns an unsigned value from 0 to 255. Subtract 80 from this value to get degrees Celsius. For example, a value of 110 indicates 30C. See Temperature Sensor. Note: Reads of this register require slower SPI timing. See Switching Characteristics. Note: This register will not return valid data unless TS_SLEEP=0. 8.91 TS_SLEEP Register (Offset = 0401h) [reset = 00h] TS_SLEEP is shown in Figure 8-78 and described in Table 8-98. Return to the Register Summary Table. Temperature Sensor Sleep Figure 8-78. TS_SLEEP Register 7 6 5 4 3 2 1 0 RESERVED TS_SLEEP R/W-00h R/W-0b Table 8-98. TS_SLEEP Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 TS_SLEEP R/W 0b If temperature conversions are not needed, set this bit to sleep the temperature sensor. 8.92 SYNC_STATUS Register (Offset = 0410h) [reset = NA] SYNC_STATUS is shown in Figure 8-79 and described in Table 8-99. Return to the Register Summary Table. Synchronization Status Figure 8-79. SYNC_STATUS Register 7 6 5 4 3 2 1 0 RESERVED CLK_REALIGN ED CLK_ALIGNED NCO_SYNC_D ET SYSREF_DET R R/W1C R R/W1C R/W1C Table 8-99. SYNC_STATUS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W NA 3 CLK_REALIGNED R/W1C NA This bit is set any time the clock dividers associated with SYSREF (excluding LMFC/LEMC) are realigned to SYSREF. This bit is useful to confirm the internally sampled SYSREF signal has a correct and stable period in DDS mode (or for debug purposes in JESD204C mode). Write a 1 to clear this bit. 2 CLK_ALIGNED R NA When set, indicates that the last SYSREF pulse was consistent with the SYSREF-associated clock dividers (except for the LMFC/LEMC). Since the LMFC/LEMC does not affect this bit, it is appropriate to use in DDS mode, but can also be used when the JESD204C interface is enabled. This bit is read-only (cannot be cleared via SPI). DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 186 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
