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DAC39RF10 Datasheet(PDF) 190 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 190 Page - Texas Instruments |
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190 / 232 page  Coarse Bias Current Control for DACA Figure 8-86. COARSE_CUR_A Register 7 6 5 4 3 2 1 0 DAC0_CBIAS_SLEEP COARSE_CUR_A R/W-0h R/W-0xF Table 8-106. COARSE_CUR_A Register Field Descriptions Bit Field Type Reset Description 7-4 DAC0_CBIAS_SLEEP R/W 0h DAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 9.1.6 3-0 COARSE_CUR_A R/W 0xF Coarse current control setting for DAC A. See Section 7.3.2.2. 8.100 FINE_CUR_B Register (Offset = 0725h) [reset = varies] FINE_CUR_B is shown in Figure 8-87 and described in Table 8-107. Return to the Register Summary Table. Fine Bias Current Control for DAC B Figure 8-87. FINE_CUR_B Register 7 6 5 4 3 2 1 0 RESERVED FINE_CUR_B R-00b R/W-varies Table 8-107. FINE_CUR_B Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 00b 5-0 FINE_CUR_B R/W varies Fine current control setting for DAC B. See Section 7.3.2.2. The default values varies to match output current specification. 8.101 COARSE_CUR_B Register (Offset = 0726h) [reset = 0Fh] COARSE_CUR_B is shown in Figure 8-88 and described in Table 8-108. Return to the Register Summary Table. Coarse Bias Current Control for DACB Figure 8-88. COARSE_CUR_B Register 7 6 5 4 3 2 1 0 DAC1_CBIAS_SLEEP COARSE_CUR_B R/W-0h R/W-0xF Table 8-108. COARSE_CUR_B Register Field Descriptions Bit Field Type Reset Description 7-4 DAC1_CBIAS_SLEEP R/W 0h DAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 9.1.6 3-0 COARSE_CUR_B R/W 0xF Coarse current control setting for DAC B. See Section 7.3.2.2. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 190 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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