DAC39RF10 datasheet(193/232 Pages) TI2

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Startup Procedure for DUC/Bypass Mode

The list below is the startup procedure for the device:

1. Power up the device with ball RESET asserted using the procedure in Section 9.3.1.

2. Apply CLK and then de-assert RESET.

3. Wait for fuse values to be loaded (register FUSE_DONE returns 1).

4. Set up all the operational parameters (registers can be programmed in any order):

a. Program interpolation factor in the DUC_L register.

b. Determine the total interpolation factor (LT), which is needed in the next steps. Except for DES1X mode

(dual edge sampling with no interpolation), LT = DUC_L.

c. Determine many sample streams are needed and program the JESD_M register.

d. Select a JESD204C mode from Table 7-22. Make sure the selected mode supports the value of LT

computed previously and the desired link layer encoding. Also make sure the mode supports the number

of desired streams set in the JESD_M register. Program the mode number into the JMODE register.

e. Program the JENC register to select 8b/10b or 64b/66b operation.

Compute the value of R using Table 7-22 and the LT value computed earlier.

g. Using Table 7-17 (8b/10b) or Table 7-18 (64b/66b), identify a row that matches the R value and DAC

clock frequency. Program REFDIV, MPY, RATE and VRANGE according to the tables.

h. If necessary, program LANE_SELn to bind the appropriate physical lanes to logical lanes. Program

LANE_INV if necessary to account for any lane inversion (differential pairs swapped on PCB).

Program other common settings according to your desired usage (SUBCLASS, SFORMAT, SCR in

JCTRL).

If using 8b/10b encoding, program the KM1 register to set the K parameter. KM1 must match the link

partner. Be sure to honor the constraint imposed by the KR parameter from Table 7-22.

k. If subclass 1 operation is desired (SUBCLASS=1), you must also program RBD. Determine the

appropriate value for RBD by referring to: Programming RBD.

Optional Serdes parameters can also be programmed if necessary (that is, JPHY_CNTL, EQ_CNTL,

EQZERO, LANE_EQn).

m. Program any DAC or DUC related registers, for example the DAC_SRC register to route data to your

desired DACs and configure MXMODE to set the DAC output mode.

5. Program the transmitter (link partner, that is, FPGA or ASIC), and instruct the transmitter to begin

transmission.

6. Program JESD_EN=1 to start up the receiver.

7. Program DP_EN=1 to enable the datapath. This is required to allow data to flow to the DAC. If only

JESD204C diagnostics are performed, you can leave DP_EN at 0.

8. Wait for the VDDDIG supply voltage to re-stablize as the supply current transient can result in a dip in the

supply voltage. 80 microseconds is be sufficient, but this can be optimized based on actual measurements.

9. If SUBCLASS=1, SYSREF is necessary to establish the LMFC/LEMC phase in the receiver. Follow this

procedure:

a. Using two separate transactions, program SYSREF_RECV_SLEEP=0 and then SYSREF_PROC_EN=1

(both in register SYSREF_CNTL).

b. Program SYSREF_SEL to a known good value (see SYSREF Windowing for details on how to calculate

SYSREF_SEL using the SYSREF windowing function).

c. Program SYSREF_ALIGN_EN=1.

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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