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DAC39RF10 Datasheet(PDF) 192 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC39RF10 Datasheet(HTML) 192 Page - Texas Instruments

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Table 8-111. DEM_DITH Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
DITHER_DACA
R/W
00b
0 : Enable single-edge dithering for DACA
1 : Enable dual-edge dithering for DACA
2 : RESERVED
3 : Dithering disabled for DACA
8.104 DAC_OFS[0:1] Register (Offset = 072Ah) [reset = 00h]
DAC_OFS[0:1] is described in Table 8-112.
Return to the Register Summary Table.
DAC Offset Control. DAC_OFS[0] is at the lowest address.
Table 8-112. DAC_OFS[0:1] Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
Reserved
R/W
000b
12-0
DAC_OFS[n]
R/W
00b
Offset adjustment for DACn (n = 0 or 1). The value in this register is
added to the DACn output. This is a 2’s complement, 13-bit signed
value. The LSB weight is one DAC LSB.
The value programmed into this register passes through a saturation
function to limit the adjustment to what is possible. If dithering is
enabled on DACn (see DEM_DITH), DAC_OFS[n] is saturated to the
range +/- 128. If dithering is disabled on DACn, the saturation range
is +/-3968.
See Section 7.3.4.
Note: This value should only be changed when DP_EN=0 or
DAC_OFS_CHG_BLK=1.
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
www.ti.com
192
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Copyright © 2026 Texas Instruments Incorporated
Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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