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d. Apply at least five SYSREF pulses to the SYSREF input. The period of each SYSREF cycle must meet

the requirements in Table 7-3.

10. Read the JESD_STATUS register to confirm operation of the link (LINK_UP field in JESD_STATUS = 1). If

the LINK_UP field returns 0, verify these items:

a. If the PLL_LOCKED field in JESD_STATUS returns 0, verify the correct PLL settings (REFDIV, MPY,

RATE and VRANGE). Verify the CLK frequency is correct.

b. If SUBCLASS = 1, and the ALIGNED field in JESD_STATUS returns 0, verify SYSREF has been applied

and the SYSREF processor is enabled SYSREF_PROC_EN.

c. If above are not the problem, then read the LANE_STATUSn (only read registers for logical lanes

0 to L-1). Identify if some lanes cannot acquire code group or block synchronization. If so, verify

the transmitter has been programmed correctly. Verify LANE_SELn is programmed correctly. Consider

performing PHY tests to verify/optimize PHY operation (PRBS testing using JTEST, eye-scan testing, or

equalizer optimization).

11. If coherency between multiple NCOs is required, the NCOs must be re-synchronized using one of the

methods described in section NCO Synchronization for multi-device/deterministic synchronization, or using

SPI_SYNC with NCO_SYNC_SRC if only internal NCO phase is required.

12. To configure the part for a different mode, set DP_EN=0 and JESD_EN=0. Then return to step 4.

9.1.2 Startup Procedure for DDS Mode

The DUC channels can operate in DDS mode by setting the DDS_EN register before setting DP_EN.

To use DDS mode, perform these steps:

1. Program DDS_EN=1 (the DDS isn’t enabled until DP_EN is set)

2. Program JESD_M to 2, 4, 6, or 8 to enable 1, 2, 3, or 4 DDS channels respectively

3. Program initial values for AMP, FREQ, and PHASE

4. There is no need to program NCO_EN (it’s implied by DDS_EN=1)

5. Program DUC_FORMAT=1 if complex output is desired. If DUC_FORMAT=1, JESD_M must be set to 2 or 4

(1 or 2 channels).

6. Program DAC_SRC to bind DUC (DDS) channels to DACs

7. Leave JESD_EN=0

8. Program DP_EN=1

9. Wait for the VDDDIG supply voltage to re-stablize as the supply current transient can result in a dip in the

supply voltage. 80 microseconds is be sufficent, but this can be optimized based on actual measurements.

10. If coherency between multiple NCO's is required, the NCO's must be re-synchronized using one of the

methods described in section NCO Synchronization for multi-device/deterministic synchronization, or using

SPI_SYNC with NCO_SYNC_SRC if only internal NCO phase is required.

11. The DUC channels now run in DDS mode and begin outputting tones. Use AMP, FREQ, and PHASE to

update the waveform parameters. You must re-synchronize the NCOs to apply new values to the NCOs. Use

AMP_R, FREQ_R, and PHASE_R to inspect the values that are currently in effect.

12. Other NCO settings also apply to DDS mode such as NCO_AR, and NCO_CONT. The NCOs can be

synchronized in the same fashion as DUC mode.

9.1.3 Understanding Dual Edge Sampling Modes

Dual edge sampling modes (DES1X, DES2XL/H) outputs unique samples on both the rising and falling edge

of CLK, doubling the sample rate for the same clock frequency compared to NRZ, RTZ or RF modes. DES1X

mode requires input samples for both clock edges while DES2XL/H modes generate the falling edge samples

by digital interpolation. The 2x DES interpolator has an 80% passband bandwidth, 55dB stopband attenuation

and can be configured as low pass or high pass (The response is shown in Figure 9-1). The DES interpolator

is lowpass in DES2XL mode, passing the signal below 0.4*FCLK and removing the image above 0.6*FCLK. IN

DES2XH mode signals above 0.6*FCLK are passed and the image below 0.4*FCLK is removed. In the transition

band between 0.4*FCLK and 0.6*FCLK, the passband is attenuated by up to 6dB and the image attenuation is

significantly reduce.

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

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