DAC39RF10 datasheet(181/232 Pages) TI2

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Table 8-82. PHASE0 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE0

R/W

Phase is added late so this register can be written during operation

to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the

phase accumulator. The phase (in radians) is PHASE0* 2-16 * 2π.

This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync

event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or

updates to the NCOs are scheduled to occur away from the change.

(See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

8.77 PHASE1 Register (Offset = 0342h) [reset = 0000h]

PHASE1 is described in Table 8-83.

Return to the Register Summary Table.

Phase for NCO1 Accumulator.

Table 8-83. PHASE1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE1

R/W

Phase is added late so this register can be written during operation

to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the

phase accumulator. The phase (in radians) is PHASE1 * 2-16 * 2π.

This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync

event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or

updates to the NCOs are scheduled to occur away from the change.

(See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

8.78 PHASE2 Register (Offset = 0344h) [reset = 0000h]

PHASE2 is described in Table 8-84.

Return to the Register Summary Table.

Phase for NCO2 Accumulator.

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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