DAC39RF10 datasheet(171/232 Pages) TI2

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Figure 8-63. DUC_FORMAT Register

RESERVED

DUC_FORMAT

R/W-00h

R/W-0b

Table 8-65. DUC_FORMAT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

DUC_FORMAT

R/W

0: DUC outputs are real (DUC mixer converts complex to real by

discarding the imaginary part). Up to 4 DUCs can be enabled.

1: DUC outputs are complex. Up to 2 DUCs can be enabled (DUC0

and DUC1).

Note: This register should only be changed when DP_EN=0.

8.62 DAC_SRC Register (Offset = 02E4h) [reset = 00h]

DAC_SRC is shown in Figure 8-64 and described in Table 8-66.

Return to the Register Summary Table.

DAC Source

Figure 8-64. DAC_SRC Register

DAC_SRC1

DAC_SRC0

R/W-0h

Table 8-66. DAC_SRC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

DAC_SRC1

R/W

When the DUCs are disabled (LT<=1), DAC_SRCn selects which

input stream is sent to DACn. When the DUCs are enabled (LT>=2),

DAC_SRCn controls which DUC outputs are routed (summed) to

DACn (and the meaning of the bits depends on DUC_FORMAT).

Signals Routed to DACn when DAC_SRCn[m] is set:

LT=0.5 or 1 (DUCs disabled)

DAC_SRCn[0]: Input Stream 0 (I)

DAC_SRCn[1]: Input Stream 1 (Q)

DAC_SRCn[2]: n/a

DAC_SRCn[3]: n/a

LT is 2 or higher (DUCs enabled) Register Bit

DAC_SRCn[x] : DUC_FORMAT=0 (real) : DUC_FORMAT=1

(complex)

DAC_SRCn[0] : DUC0 (real) : DUC0 (real)

DAC_SRCn[1] : DUC1 (real) : DUC1 (real)

DAC_SRCn[2] : DUC2 (real) : DUC0 (imag)

DAC_SRCn[3] : DUC3 (real) : DUC1 (imag)

If more than one signal is routed to the same DAC, the signals are

summed together. Use DUC_GAIN to avoid saturation in this case.

While it is possible to sum a real output with an imaginary output,

no practical application requires that, so it is not tested or supported.

When LT=0.5 or 1, no summing is supported. Only DAC_SRCn[0] or

DAC_SRCn[1] should be set

Note: This register should only be changed when DP_EN=0.

3-0

DAC_SRC0

R/W

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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