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DAC39RF10 Datasheet(PDF) 167 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 167 Page - Texas Instruments |
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167 / 232 page  Table 8-56. CDRPHASE Register Field Descriptions Bit Field Type Reset Description 7-0 CDRPHASE R Returns the current CDR phase value for the lane specified by RXDLANE. It is recommended to set CDRLOCK=1 before reading this register. The format is gray-coded. Refer to CDRPHASE Status for the coding. 8.54 PLL_STATUS Register (Offset = 0250h) [reset = NA, read only] PLL_STATUS is shown in Figure 8-7 and described in Table 8-8. Return to the Register Summary Table. SerDes PLL Status Figure 8-55. PLL_STATUS Register 7 6 5 4 3 2 1 0 PLL_LOCK_STS PLL_LOCK_LOST R-0h R/W1C-0h Table 8-57. PLL_STATUS Register Field Descriptions Bit Field Type Reset Description 7-4 PLL_LOCK_STS R 0h This field returns the LOCK signal from all four SerDes macros (3:0). This field can be used for functional (fault) testing of the PLL lock detectors. 3-0 PLL_LOCK_LOST R/W1C 0h PLL_LOCK_LOST[n] is set whenever the LOCK signal from a SerDes PLL is low. bit 0: lanes 0 - 3 bit 1: lanes 4 - 7 bit 2: lanes 8 - 11 bit 3: lanes 12 - 15 This bit is sticky (remains set even if the PLL acquires lock). Write 1 to clear a bit. These bits are for debug purposes and allow the SPI to monitor if any SerDes PLL loses lock even briefly. 8.55 JESD_RST Register (Offset = 0253h) [reset = 0x00] JESD_RST is shown in Figure 8-56 and described in Table 8-58. Return to the Register Summary Table. JESD Reset Figure 8-56. JESD_RST Register 7 6 5 4 3 2 1 RESERVED JESD_RST R/W-00h R/W-0h Table 8-58. JESD_RST Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h RESERVED www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 167 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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