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DAC39RF10 Datasheet(PDF) 169 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 169 Page - Texas Instruments |
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169 / 232 page  Figure 8-59. DAC_OFS_CHG_BLK Register 7 6 5 4 3 2 1 0 RESERVED DAC_OFS_CH G_BLK R/W-00h R/W-0b Table 8-61. DAC_OFS_CHG_BLK Register Field Descriptions Bit Field Type Reset Description 7-1 R/W 00h 0 DAC_OFS_CHG_BLK R/W 0b When set, changes to DAC_OFS[n] are not propagated to the high- speed clocks and both DACs continue to use their current value. When this is changed from 1 to 0 the new DAC_OFS[n] values will be applied to both DACs in the same clock cycle. 8.58 DP_EN Register (Offset = 02E0h) [reset = 00h] DP_EN is shown in Figure 8-60 and described in Table 8-62. Return to the Register Summary Table. Datapath Enable. Figure 8-60. DP_EN Register 7 6 5 4 3 2 1 0 RESERVED DP_EN R/W-00h R/W-0b Table 8-62. DP_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 DP_EN R/W 0b Setting this bit enables datapath operation. When cleared, the datapath is held in reset. This bit should be set after the chip is configured for proper operation. Note: This register should only be changed from 0 to 1 when FUSE_DONE=1. 8.59 DUC_L Register (Offset = 02E1h) [reset = 00h] DUC_L is shown in Figure 8-61 and described in Table 8-63. Return to the Register Summary Table. DUC Interpolation Factor. Figure 8-61. DUC_L Register 7 6 5 4 3 2 1 0 RESERVED DUC_L R/W-0h R/W-0h Table 8-63. DUC_L Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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