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DAC39RF10 Datasheet(PDF) 165 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 165 Page - Texas Instruments |
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165 / 232 page  8.49 ESCOUNT[15:0] Register (Offset = 0210h) [reset = NA, read-only] ESCOUNT[15:0] is shown in Figure 8-50 and described in Table 8-52. Return to the Register Summary Table. Eye-Scan Voltage Offset for SerDes lane n, n = 0 - 15. ESCOUNT[0] is at the lowest address. Figure 8-50. ESCOUNT[15:0] Register 7 6 5 4 3 2 1 0 ESCOUNT[15:8][n] R ESCOUNT[7:0][n] R Table 8-52. ESCOUNT[15:0] Register Field Descriptions Bit Field Type Reset Description 15-0 ESCOUNT[n] R NA Returns the mismatch count for physical lane n (applies to eye-scan modes that count mismatches). Only valid when ESDONE[n] returns 1. 8.50 LOS_TH Register (Offset = 0234h) [reset = 08h] LOS_TH is shown in Figure 8-51 and described in Table 8-53. Return to the Register Summary Table. SerDes Loss-of-signal Theshold Figure 8-51. LOS_TH Register 7 6 5 4 3 2 1 0 RESERVED LOS_TH R/W-0h R/W-0h Table 8-53. LOS_TH Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 LOS_TH R/W 0h Specifies the threshold for the loss-of-signal detector. Applies when LOS_EN=1. Affects all lanes. LOS_TH : Approximate Threshold (mV) 0, 1 : RESERVED 2 - 15 : 15*(LOS_TH) 8.51 EQCNTSZ Register (Offset = 0235h) [reset = 00h] EQCNTSZ is shown in Figure 8-52 and described in Table 8-54. Return to the Register Summary Table. SerDes Equalizer Counter Size Figure 8-52. EQCNTSZ Register 7 6 5 4 3 2 1 0 R/W-0h R/W-0h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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