DAC39RF10 datasheet(205/232 Pages) TI2

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1 GHz

Ref In

DRO

-2V

THS4031

SIM-153LH+

EP2C+

To DAC

Clock

Distribution

Figure 9-9. Discrete Analog PLL

The APLL outperforms the previous examples by avoiding use of digital dividers and phase detectors, which

significantly degrade phase noise. Instead passive diode-based frequency multipliers and mixers are used,

which contribute little additive phase noise. Like all synthesizers, a frequency reference with very good close in

phase noise, below the loop bandwidth of the APLL, is required for best performance.

In this case, a 1GHz reference was chosen as the reference is a convenient division of the sample rate and

is available either as an output of an R&S SMA100B RF signal generator or as a standalone unit from Wenzel

Associates.

As mentioned previously, the APLL does not use digital dividers or phase detectors, which significantly degrade

phase noise. Instead the reference is multiplied up to the output frequency using passive multiplier stages (see

Figure 9-10). A passive mixer is used as a phase detector that feeds a low noise operational amplifier loop filter.

The DRO output is split with one output going to the DAC clock distribution network and the other feeding back

into the RF port of the mixer.

SYK-2R+

PSA-14+

2 GHz

1 GHz

Ref In

1.2 GHz

PSA-14+

EP2C+

2 GHz

Ref Out

CY2-143+

PSA-14+

4 GHz

2.75 GHz

PSA-14+

EP2C+

4 GHz

Ref Out

CY2-143+

PSA-14+

8 GHz

4.4 GHz

PMA2-183LN+

8 GHz

Ref Out

Figure 9-10. Reference Multiplier Chain

The multiplier chain uses low noise amplifiers, passive diode multipliers and bandpass filters. For this part of the

circuit, what is most critical is the close in phase noise below the loop bandwidth of the PLL. Not all amplifiers

demonstrate good close in noise, especially when driven near or into compression. Generally, heterojunction

bipolar transistor (HBT) amplifiers, have low flicker noise and operate well when driven into compression.

Bandpass filters were selected to remove the FIN and 3 x FIN/2 harmonics that are only partially suppressed

by the multipliers. In some implementations the driving amplifier can be filtered to prevent degradation of

the harmonic suppression performance. This chain was experimentally optimized, but additional attenuation

between stages can be added to manage reflections and amplifier operating conditions.

The loop filter bandwidth is set near where the open loop DRO phase noise crosses the multiplied reference

noise with a damping factor set to give a smooth role off that minimizes integrated phase noise. An optional

additional feedback cap can be used to speed up the role off if desired (C2 is set roughly to 1/10th to 1/100th of

C1). The loop filter component values were determined experimentally for this design.

In some implementations a start-up circuit is needed to help the loop acquire lock. In practice, the initial power

up was all that is needed for the loop to pull in and lock.

9.2.4.4 10GHz Clock Generation

For higher sample rates several options are available. First, a DRO can be selected that operates directly at the

desired frequency and the multiplier chain and or reference frequency can be modified accordingly.

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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