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DAC39RF10 Datasheet(PDF) 203 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC39RF10 Datasheet(HTML) 203 Page - Texas Instruments

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Figure 9-6. Phase Noise of DAC Clock Examples with the Device Additive Phase Noise
9.2.4.1 Example 1: SWAP-C Optimized
The best SWAP-C sub-system leverages the high levels of integration offered by modern PLL+VCO devices,
such as the LMX2820. Figure 9-7 shows a block diagram of the clocking sub-system. An external reference
clock feeds the LMX2820 input, which is then used to lock the internal PLL+VCO before being fed to the output
buffers. Only external passives are required to construct the loop filter and complete the sub-system system.
PFD + CP
VCO
Loop
Filter
/1
/N
x2
/N
LMX2820
400 MHz
Ref In
/20
To DAC
Clock
Distribution
Figure 9-7. LMX2820 with Internal VCO
The LMX2820 is a flexible device and configuration can be overwhelming. For example, deciding how to
decipher configure dividers, set loop filter components, and so on. A few high-level guidelines can be taken into
consideration to optimize phase noise.
First,always operate the LMX2820 in integer mode when possible, as opposed to fractional mode. This implies
that relationship between reference clock and output clock follows the general form:
FOUT = (FREF/NREF) x NDIV/NOUT
(5)
where NREF, NDIV and NOUT are the reference, feedback and output dividers respectively. FREF is the input
reference frequency and FOUT is the output frequency used as the DAC clock. If this ratio cannot be found, then
fractional mode must be used at the expense of degraded overall phase noise.
Second, the best in-band phase noise is achieved when the phase detector frequency is maximized and the
feedback divider is minimized. The LMX2820 has a maximum phase detector frequency of 400MHz and an
optional reference doubler is available for reference inputs up to 200MHz. For the same output frequency, each
doubling of phase detector frequency (while halving the feedback divider) results in 3dB of in band phase noise
reduction.
www.ti.com
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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