DAC39RF10 datasheet(200/232 Pages) TI2

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Table 9-2. Summary of Radiation Tolerance (continued)

Feature

Radiation Tolerance

Read-only SPI status registers associated with JESD204C physical

or link layers (excluding write-to-clear registers)

The value returned can be affected by radiation

(SYSREF_POS, LINK_UP, JSYNC_STATE, PLL_LOCKED,

LANE_ARR, FIFO_STATUS, JCAP_STATUS, JCAP, BER_CNT,

LANE_EQS, ESDONE, ESVO_S, ECOUNT, RXDMUX, CDRPHASE,

RXCSA_S).

FUSE_DONE register

FUSE_DONE is upset-immune.

OCSTS register

Once the PHY is initialized and offset calibration is completed,

OCSTS returns offset values that are upset immune. However, an

upset can cause a PHY PLL to lose lock which can re-trigger the

offset calibration process, generating new offset calibration values.

Sticky SPI status registers

(write-to-clear)

These bits are set when certain events occur in upset-vulnerable

logic. An upset can cause the event to occur, and set the sticky

bit. An upset can also prevent an event from setting the sticky bit;

however this is unlikely as the window of time that this can occur is

small. Once the sticky bit is set, an upset does not clear the bit (the

flop that is read by SPI is upset immune).

Examples: LANE_ERR, PLL_LOCK_LOST, SYS_ALM,

REALIGNED, CLK_REALIGNED.

JESD204C Receiver

The JESD204C receiver is not upset immune, but is designed to

be free from functional interrupts (can recover automatically from

upsets). See JESD204C Reliability.

Interpolation Filters (DUC and DES2X filters)

The interpolation filters are not upset immune and can generate

glitches when upset. The filters do not suffer from functional

interrupts.

NCOs in DUCs

The radiation sensitivity of the NCO is TBD.

Temperature Sensor

The ADC inside the temperature sensor is not upset immune. To

improve reliability, the recommendation is to read TS_TEMP three or

more times, and compute the median value.

9.1.7.1 SPI Programming

The SPI interface and register set are implemented with upset immune logic. The state of writable SPI registers

will not be altered by radiation. The Fast-Reconfiguration interface is not upset immune and should not be

enabled in radiation environments.

9.1.7.2 JESD204C Reliability

The JESD204C receiver is implemented with high speed flip-flops that are not single-upset-immune. As a result,

the JESD204C link can experience various errors when exposed to radiation.

To improve the overall reliability of the link and make sure the link can automatically recover from an upset,

several recommendations should be followed.

1. Use subclass 1 operation by setting SUBCLASS=1.

2. 64b/66b link encoding (JENC=1) is preferred over 8b/10b encoding. The 64b/66b link layer provides full-time

block and EMB synchronization (pilot) signals, so misalignment caused by radiation can be detection quickly

and consistently. In contrast, the 8b/10b link layer relies on synchronization characters that do not have a

high occurrence rate, so misalignment takes longer to detect.

3. Use a periodic and continuous SYSREF signal. Keep SYSREF alignment enabled at all times in the Tx

and Rx devices. If radiation upsets the Tx or Rx LMFC/LEMC, the SYSREF signal will re-establish their

phase and keep the Rx and Tx synchronized. If this recommendation is not followed, radiation can cause a

persistent change in the link latency, or cause lanes to be persistently misaligned (causing persistent, corrupt

samples to be sent to the DAC).

4. 4. The transmitting logic device that provides data to the SerDes receiver should be designed with radiation

tolerance in mind. Recommendations include:

a. When possible, align counters continuously to SYSREF.

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

200

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