DAC39RF10 datasheet(204/232 Pages) TI2

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For an 8GHz output, use the maximum phase detector frequency of 400MHz. Set NREF = 1, NDIV = 20, and NOUT

= 1 (divider bypass). For a slight degradation in in-band noise, the input can be set to 200MHz and the reference

doubler is used.

Third, note that any noise on the reference input impacts close in phase noise before the in-band noise begins

to dominate. In-band noise is a combination of PLL noise (phase detector, charge pump and dividers) and

VCO noise, while wideband noise is limited by the noise floor of the output buffers. Close in noise is limited

by the device flicker, which is independent of phase detector frequency and scales 20 x LOGbase10 with output

frequency.

Finally, when operating the LMX2820 above 11GHz, the integrated output doubler must be used and this results

in a sub-harmonic (that is, output frequency divided by 2) that possibly requires external filtering using either a

high-pass or bandpass filter (depending on system requirements). Following the LMX2820 output with a narrow

bandpass filter can also be used to suppress wideband noise.

The PLLatinumSim software is available from TI to design the external loop filter passive values.

9.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO

An external VCO can significantly improve in-band and wideband noise, with best phase noise typically achieved

with narrow band VCOs such as Voltage Controlled Crystal Oscillators (VCXO), Voltage Controlled Surface

Acoustic Wave Oscillators (VCSO) and Dielectric Resonance Oscillators (DRO). For this design, a Synergy

Microwave 8GHz DRO (SDRO800-8), is used for the wideband noise (-170dBc/Hz) and low flicker noise corner

(-160dBc/Hz at 1MHz). DROs are typically available from about 5 to over 25GHz.

Figure 9-8 shows a block diagram of the synthesizer. An external active loop filter is used to improve noise

performance and extend the tuning voltage range required for the DRO (0 to 10V). The DROs output is split, with

one output feeding back into the LMX2820 and the other being sent to the DAC clock distribution network.

PFD + CP

LMX2820

400 MHz

Ref In

/20

-2V

THS4031

390

68nF

1.5nF

+1.2V

VCO

DRO

EP2C+

To DAC

Clock

Distribution

Figure 9-8. External LMX2820 with an External VCO

In this implementation, the loop bandwidth was set to around 24kHz, where the flicker noise of the PLL intersects

the open loop noise of the DRO. This offers the best overall integrated phase noise. The noise floor is improved

by about 10dB from the fully integrated example since the output buffers were not used and the DRO has

exceptional broadband noise of around -170dBc/Hz.

As with the integrated VCO, the loop filter components can be designed using PLLatinumSim software.

9.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance

When phase noise performance is paramount, a discrete analog PLL (APLL) offers substantially lower phase

noise than the integrated examples. The trade off is increased SWAP-C. Figure 9-9 shows the block diagram

of such an implementation that uses the same Synergy Microwave 8GHz DRO as the LMX2820 external VCO

example discussed previously.

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

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