DAC39RF10 datasheet(202/232 Pages) TI2

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return signal from a small moving object. This places a requirement on close in phase noise for the close in

phase noise of the radar chirp.

Radars are also sensitive to spurious signals, and for this example, assume 90dBFS is required for the inband

SFDR.

9.2.3 Detailed Design Procedure

A summary of the design parameters are listed in Table 9-3. A input sample rate of 250MSPS complex covers

the 200MHz signal bandwidth, and interpolation by 32x is used to increase the TX sample rate to 8GSPS. The

device's numerically controlled oscillator (NCO) is used to place the signal at the TX output at 3.2GHz. An

addition 2x interpolation is applied in DES2XL mode, increasing the sample rate to 16GSPS.

The suppression of the image at 4.7 - 4.9GHz in DES2XL mode would be limited by the 2x DES interpolator to

40dB.

To optimize the low offset frequency phase noise, DEM and dither are disabled.

The JESD204C interface is configured in JMODE 5 with 4 streams (2 IQ pairs) and 1 Serdes lane per IQ pair.

With 64/66 bit encoding, the Serdes baud rate is 8.25Gbps.

Table 9-3. Design Parameters for an S-band Transmitter

Parameter

Value

Input Clock

8GHz

DAC Sample Rate

16GSPS

Output Mode

DES2XL

DEM and Dither Settings

Off

TX Interpolation Factor

32x

TX Input Rate

250MSPS Complex

NCO frequency

3.2GHz

JMODE

# Streams

4 (2x IQ pairs, 1/DAC)

# Serdes Lanes

Encoding

64/66

Serdes Baud Rate

8.25Gbps

9.2.4 Detailed Clocking Subsystem Design Procedure

One of the major advantages of the DAC39RF10-Sx and 'RFS10-Sx in applications like Doppler radar, Quantum

Computing and Wireless Test is the ability to directly synthesize very low phase noise signals all the way

through X-band (12GHz). To take full advantage of the exceptionally low additive phase noise of the DAC, a

high-performance clock is required.

Equally important in most systems is the impact of Size, Weight, Area, Power and Cost (SWAP-C). This means

each system architect must weight tradeoffs in performance vs. overall system SWAP-C based on system

requirements. This section presents three clocking examples based on SWAP-C vs. performance tradeoffs.

Figure 9-6 shows a plot of phase noise for an 8GHz sample clock produced by an integrated PLL+VCO,

integrated PLL with external high performance VCO and a fully discrete high performance analog PLL. All

examples assume a reference clock is provided as an input to the synthesizer, which can range from low

cost surface mount crystal oscillators all the way to expense reference subsystems. The DAC39RF10-Sx and

'RFS10-Sx additive phase noise at 8GHz is also provided for comparison , even for the analog PLL, the clock

phase noise degrades the DAC39RF10-Sx and 'RFS10-Sx output phase noise for offset frequencies below

5MHz.

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

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