C8051F310 datasheet(92/228 Pages) SILABS

92 / 228 page

C8051F310/1/2/3/4/5/6/7

Rev. 1.7

SFR Definition 8.4. PSW: Program Status Word

SFR Definition 8.5. ACC: Accumulator

Bit7:

CY: Carry Flag.

This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow

(subtraction). It is cleared to logic 0 by all other arithmetic operations.

Bit6:

AC: Auxiliary Carry Flag

This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow

from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic opera-

tions.

Bit5:

F0: User Flag 0.

This is a bit-addressable, general purpose flag for use under software control.

Bits4–3: RS1–RS0: Register Bank Select.

These bits select which register bank is used during register accesses.

Bit2:

OV: Overflow Flag.

This bit is set to 1 under the following circumstances: an ADD, ADDC, or SUBB instruction

causes a sign-change overflow, a MUL instruction results in an overflow (result is greater

than 255), or a DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0

by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.

Bit1:

F1: User Flag 1.

This is a bit-addressable, general purpose flag for use under software control.

Bit0:

PARITY: Parity Flag.

This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the

sum is even.

R/W

Reset Value

RS1

RS0

PARITY

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

0xD0

RS1

RS0

Address

0x00–0x07

0x08–0x0F

0x10–0x17

0x18–0x1F

Bits7–0: ACC: Accumulator.

This register is the accumulator for arithmetic operations.

R/W

Reset Value

ACC.7

ACC.6

ACC.5

ACC.4

ACC.3

ACC.2

ACC.1

ACC.0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

0xE0

C8051F310 Datasheet(PDF) 92 Page - Silicon Laboratories

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