C8051F310 datasheet(93/228 Pages) SILABS

93 / 228 page

Rev. 1.7

C8051F310/1/2/3/4/5/6/7

SFR Definition 8.6. B: B Register

8.3.

Interrupt Handler

The CIP-51 includes an extended interrupt system supporting a total of 14 interrupt sources with two prior-

ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies

according to the specific version of the device. Each interrupt source has one or more associated interrupt-

pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,

the associated interrupt-pending flag is set to logic 1.

If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is

set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-

termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI

instruction, which returns program execution to the next instruction that would have been executed if the

interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the

hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-

less of the interrupt's enable/disable state.)

Each interrupt source can be individually enabled or disabled through the use of an associated interrupt

enable bit in an SFR (IE-EIE1). However, interrupts must first be globally enabled by setting the EA bit

(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables

all interrupt sources regardless of the individual interrupt-enable settings.

Note: Any instruction that clears the EA bit should be immediately followed by an instruction that

has two or more opcode bytes. For example:

// in 'C':

EA = 0;

// clear EA bit

EA = 0;

// ... followed by another 2-byte opcode

; in assembly:

CLR

; clear EA bit

CLR

; ... followed by another 2-byte opcode

If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears

the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. How-

ever, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is

followed by a multi-cycle instruction, the interrupt will not be taken.

Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.

However, most are not cleared by the hardware and must be cleared by software before returning from the

ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)

Bits7–0: B: B Register.

This register serves as a second accumulator for certain arithmetic operations.

R/W

Reset Value

B.7

B.6

B.5

B.4

B.3

B.2

B.1

B.0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

0xF0

C8051F310 Datasheet(PDF) 93 Page - Silicon Laboratories

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