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TMS320DM641 Datasheet(PDF) 161 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 161 Page - Texas Instruments |
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161 / 179 page  Ethernet Media Access Controller (EMAC) 161 June 2003 − Revised October 2005 SPRS222E Table 4−69. Timing Requirements for EMAC MII Receive 10/100 Mbit/s† (see Figure 4−58) NO. −400 −500 −600 UNIT MIN MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns † Receive selected signals include: MRXD3−MRXD0, MRXDV, and MRXER. MRCLK (Input) 1 2 MRXD3−MRXD0, MRXDV, MRXER (Inputs) Figure 4−58. EMAC Receive Interface Timing Table 4−70. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s‡ (see Figure 4−59) NO. −400 −500 −600 UNIT MIN MAX 1 td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid 5 25 ns ‡ Transmit selected signals include: MTXD3−MTXD0, and MTXEN. 1 MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) Figure 4−59. EMAC Transmit Interface Timing |
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