EM78P341 datasheet(33/102 Pages) EMC

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EM78P341N/342N/343N

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 12.01.2006

• 27

(This specification is subject to change without further notice)

6.2.16 IOC91 (Low-Time Register)

The 8-bit Low-time register controls the active or Low segment of the pulse.

The decimal value of its contents determines the number of oscillator cycles and

verifies that the IR OUT pin is active. The active period of IR OUT can be calculated as

follows:

NOTE

■ Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale (IOCB1) } / FT

■ FT is system clock: FT = Fosc/1 (CLK=2)

FT = Fosc/2 (CLK=4)

When an interrupt is generated by the Low time down counter underflow (if enabled),

the next instruction will be fetched from address 015H (Low time).

6.2.17 IOCA1 (High Time Register)

The 8-bit High-time register controls the inactive or High period of the pulse.

The decimal value of its contents determines the number of oscillator cycles and

verifies that the IR OUT pin is inactive. The inactive period of IR OUT can be calculated

as follows:

NOTE

■ High time width = {[1+decimal high-time value (IOCA1)] * High time Scale (IOCB1) } / FT

■ FT is system clock: FT=Fosc/1(CLK=2)

FT=Fosc/2(CLK=4)

When an interrupt is generated by the High time down counter underflow (when

enabled), the next instruction will be fetched from Address 012H (High time).

6.2.18 IOCB1 High/Low Time Scale Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HTSE

HTS2

HTS1

HTS0

LTSE

LTS2

LTS1

LTS0

Bit 7 (HTSE): High-time scale enable bit

0 = scale disable bit, High-time rate is 1:1

1 = scale enable bit, High-time rate is set as Bit 6~Bit 4.

EM78P341 Datasheet(PDF) 33 Page - ELAN Microelectronics Corp

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