EM78P341 datasheet(87/102 Pages) EMC

87 / 102 page

EM78P341N/342N/343N

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 12.01.2006

• 81

(This specification is subject to change without further notice)

6.15 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one

or more operands. Normally, all instructions are executed within one single instruction

cycle (one instruction consists of two oscillator periods), unless the program counter is

changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or

logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,

these instructions need one or two instruction cycles as determined by the Code Option

In addition, the instruction set has the following features

1. Every bit of any register can be set, cleared, or tested directly.

2. The I/O registers can be regarded as general registers. That is, the same

instruction can operate on I/O registers.

The following symbols are used in the Instruction Set table

Convention:

R = Register designator that specifies which one of the registers (including operation and general purpose

registers) is to be utilized by the instruction.

Bits 6 and 7 in R4 determine the selected register bank.

b = Bit field designator that selects the value for the bit located in the register R and which affects the

operation.

k = 8 or 10-bit constant or literal value

Binary Instruction

Hex

Mnemonic

Operation

Status Affected

0 0000 0000 0000 0000

NOP

No Operation

None

0 0000 0000 0001 0001

DAA

Decimal Adjust A

0 0000 0000 0010 0002

CONTW

→ CONT

None

0 0000 0000 0011 0003

SLEP

→ WDT, Stop oscillator

T, P

0 0000 0000 0100 0004

WDTC

→ WDT

T, P

0 0000 0000 rrrr

000r

IOW R

→ IOCR

None

0 0000 0001 0000 0010

ENI

Enable Interrupt

None

0 0000 0001 0001 0011

DISI

Disable Interrupt

None

0 0000 0001 0010 0012

RET

[Top of Stack]

→ PC

None

0 0000 0001 0011 0013

RETI

[Top of Stack]

→ PC,

Enable Interrupt

None

0 0000 0001 0100 0014

CONTR

CONT

→ A

None

0 0000 0001 rrrr

001r

IOR R

IOCR

→ A

None

0 0000 01rr rrrr

00rr

MOV R,A

→ R

None

0 0000 1000 0000 0080

CLRA

→ A

0 0000 11rr rrrr

00rr

CLR R

→ R

0 0001 00rr rrrr

01rr

SUB A,R

R-A

→ A

Z, C, DC

0 0001 01rr rrrr

01rr

SUB R,A

R-A

→ R

Z, C, DC

0 0001 10rr rrrr

01rr

DECA R

R-1

→ A

0 0001 11rr rrrr

01rr

DEC R

R-1

→ R

0 0010 00rr rrrr

02rr

OR A,R

∨ VR → A

0 0010 01rr rrrr

02rr

OR R,A

∨ VR → R

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