Data Sheet

AD5172/AD5173

SPECIFICATIONS

analog.com

Rev. J | 5 of 22

Table 2.

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

Input Logic Low9

VIL

VDD = 5 V

−0.5

+0.3 VDD

V

AD0 and AD1

Input Logic High

VIH

VDD = 3 V

2.1

V

Input Logic Low

VIL

VDD = 3 V

0.6

V

Input Current

IIL

VIN = 0 V or 5 V

±1

µA

Input Capacitance7

CIL

5

pF

POWER SUPPLIES

Power Supply Range

VDD

2.7

5.5

V

OTP Supply Voltage9, 10

VDD_OTP

TA = 25°C

5.6

5.7

5.8

V

Supply Current

IDD

VIH = 5 V or VIL = 0 V

3.5

6

µA

OTP Supply Current9, 11, 12

IDD_OTP

VDD_OTP = 5.7 V, TA = 25°C

100

mA

Power Dissipation13

PDISS

VIH = 5 V or VIL = 0 V, VDD = 5

V

33

µW

Power Supply Sensitivity

PSS

VDD = 5 V ± 10%, code =

midscale

±0.02

±0.08

%/%

DYNAMIC CHARACTERISTICS14

Bandwidth, −3 dB

BW

RAB = 10 kΩ, code = 0x80

600

kHz

RAB = 100 kΩ, code = 0x80

40

kHz

Total Harmonic Distortion

THDW

VA = 1 V rms, VB = 0 V, f = 1

kHz, RAB = 10 kΩ

0.1

%

VW Settling Time

tS

VA = 5 V, VB = 0 V, ±1 LSB

error band

2

µs

Resistor Noise Voltage Density

eN_WB

RWB = 5 kΩ, RS = 0 Ω

9

nV/√Hz

1 Typical specifications represent average readings at 25°C and VDD = 5 V.

2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3 VA = VDD, VB = 0 V, wiper (VW) = no connect.

4 Specifications apply to all VRs.

5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions.

6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

7 Guaranteed by design, but not subject to production test.

8 Measured at Terminal A. Terminal A is open circuited in shutdown mode.

9 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up

to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up

resistors.

10 Different from the operating power supply; the power supply for OTP is used one time only.

11 Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.

12 See Figure 29 for an energy plot during an OTP program.

13 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

14 All dynamic characteristics use VDD = 5 V.