AD5172 datasheet(15/22 Pages) AD

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Data Sheet

AD5172/AD5173

THEORY OF OPERATION

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Rev. J | 15 of 22

The general equation that determines the digitally programmed

output resistance between W and B is

RWBD = D256×RAB+2×RW

(1)

where:

D is the decimal equivalent of the binary code loaded in the 8-bit

RDAC register.

RAB is the end-to-end resistance.

RW is the wiper resistance contributed by the on resistance of the

internal switch.

In summary, if RAB is 10 kΩ and the A terminal is open circuited, the

output resistance, RWB, is set according to the RDAC latch codes,

as listed in Table 8.

Table 8. Codes and Corresponding RWB Resistance

D (Dec)

RWB (Ω)

Output State

255

10,281

Full scale (RAB – 1 LSB + 2 × RW)

128

5320

Midscale

359

1 LSB

320

Zero scale (wiper contact resistance)

Note that in the zero-scale condition, a finite wiper resistance of

160 Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum pulse current of no

more than 20 mA. Otherwise, degradation or possible destruction of

the internal switch contact may occur.

Similar to the mechanical potentiometer, the resistance of the

RDAC between Wiper W and Terminal A also produces a digitally

controlled complementary resistance, RWA. When these terminals

are used, the B terminal can be opened. Setting the resistance val-

ue for RWA starts at a maximum value of resistance and decreases

as the data loaded in the latch increases in value. The general

equation for this operation is

RWAD =256–D256×RAB+2×RW

(2)

When RAB is 10 kΩ and the B terminal is open circuited, the output

resistance, RWA, is set according to the RDAC latch codes, as listed

in Table 9.

Table 9. Codes and Corresponding RWA Resistance

D (Dec)

RWA (Ω)

Output State

255

359

Full scale

128

5320

Midscale

10,281

1 LSB

10,320

Zero scale

Typical device-to-device matching is process lot dependent and can

vary up to ±30%. Because the resistance element is processed

using thin film technology, the change in RAB with temperature has

a very low temperature coefficient of 35 ppm/°C.

PROGRAMMING THE POTENTIOMETER

DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at wiper

to B and at wiper to A, proportional to the input voltage at A to B.

Unlike the polarity of VDD to GND, which must be positive, voltage

across A to B, W to A, and W to B can be at either polarity.

Figure 41. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper to B, starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across Terminal A and Terminal B divided by the

256 positions of the potentiometer divider. The general equation

defining the output voltage at VW with respect to ground for any

valid input voltage applied to Terminal A and Terminal B is

VW(D)= D256VA+256−D256VB

(3)

A more accurate calculation, which includes the effect of wiper

resistance, VW, is

VW(D)=RWB(D)RABVA+RWA(D)RABVB

(4)

Operation of the digital potentiometer in the divider mode results in

more accurate operation over temperature. Unlike in the rheostat

mode, the output voltage is dependent mainly on the ratio of

the internal resistors, RWA and RWB, not on the absolute values.

Therefore, the temperature drift reduces to 15 ppm/°C.

ESD PROTECTION

All digital inputs, SDA, SCL, AD0, and AD1, are protected with a

series input resistor and parallel Zener ESD structures, as shown in

Figure 42 and Figure 43.

Figure 42. ESD Protection of Digital Pins

Figure 43. ESD Protection of Resistor Terminals

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