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Data Sheet

AD5172/AD5173

THEORY OF OPERATION

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Rev. J | 16 of 22

TERMINAL VOLTAGE OPERATING RANGE

The AD5172/AD5173 to GND power supply defines the boundary

conditions for proper 3-terminal digital potentiometer operation.

Supply signals present on Terminal A, Terminal B, and Terminal

W that exceed VDD or GND are clamped by the internal forward-

biased diodes (see Figure 44).

Figure 44. Maximum Terminal Voltages Set by VDD and GND

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at Terminal A, Terminal B, and Terminal W (see Figure 44), it is

important to power VDD/GND before applying voltage to Terminal A,

Terminal B, and Terminal W. Otherwise, the diode is forward-biased

such that VDD is powered unintentionally and may affect the rest

of the user’s circuit. The ideal power-up sequence is GND, VDD,

digital inputs, and then VA/VB/VW. The relative order of powering

VA, VB, VW, and the digital inputs is not important, as long as they

are powered after VDD/GND.

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both the one-time programming

and normal operating voltage supplies are applied to the same

VDD terminal of the device. The AD5172/AD5173 employ fuse link

technology that requires 5.6 V to 5.8 V to blow the internal fuses to

achieve a given setting, but normal VDD can be 2.7 V to 5.5 V. Such

dual-voltage requirements need isolation between the supplies if

VDD is lower than the required VDD_OTP. The fuse programming

supply (either an on-board regulator or rack-mount power supply)

must be rated at 5.6 V to 5.8 V and must be able to provide a

100 mA transient current for 400 ms for successful one-time pro-

gramming. When programming is completed, the VDD_OTP supply

must be removed to allow normal operation at 2.7 V to 5.5 V; the

device consumes only microamps of current.

Figure 45. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply

For example, for those who operate their systems at 2.7 V, use

of the bidirectional, low threshold, P-channel MOSFETs is recom-

mended for the isolation of the supply. As shown in Figure 45, this

assumes that the 2.7 V system voltage is applied first and that

the P1 and P2 gates are pulled to ground, thus turning on P1 and

then P2. As a result, VDD of the AD5172/AD5173 approaches 2.7

V. When the AD5172/AD5173 setting is found, the factory tester

applies the VDD_OTP to both the VDD and the MOSFET gates, thus

turning P1 and P2 off. To program the AD5172/AD5173 while the

2.7 V source is protected, execute the OTP command at this time.

When the OTP is completed, the tester withdraws the VDD_OTP, and

the setting of the AD5172/AD5173 is fixed permanently.

The AD5172/AD5173 achieve the OTP function by blowing internal

fuses. Always apply the 5.6 V to 5.8 V one-time program voltage

requirement at the first fuse programming attempt. Failure to com-

ply with this requirement may lead to changing the fuse structures,

rendering programming inoperable.

Care should be taken when SCL and SDA are driven from a low

voltage logic controller. Users must ensure that the logic high level

is between 0.7 V × VDD and VDD + 0.5 V.

Poor PCB layout introduces parasitics that can affect fuse program-

ming. Therefore, it is recommended to add a 1 µF to 10 µF tantalum

capacitor in parallel with a 1 nF ceramic capacitor as close as

possible to the VDD pin. The type and value chosen for both

capacitors are important. These capacitors work together to provide

both fast responsiveness and large supply current handling with

minimum supply droop during transients. As a result, these capaci-

tors increase the OTP programming success by not inhibiting the

proper energy needed to blow the internal fuses. Additionally, C1

minimizes transient disturbance and low frequency ripple, whereas

C2 reduces high frequency noise during normal operation.

Figure 46. Power Supply Bypassing

LAYOUT CONSIDERATIONS

In PCB layout, it is a good practice to employ compact, minimum

lead length design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths should

have low resistance and low inductance.

Note that the digital ground should also be joined remotely to the

analog ground at one point to minimize the ground bounce.

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