CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

26

®Copyright 2008 Cirrus Logic, Inc.

DS705PP2

5.20 Switching Characteristics — External Memory Interface - Flash Mode

Parameter

Symbol

Min

Max

Unit

Write Cycle

Address Setup time to EXT_WE# falling

1.2 * DCLKP

ns

1. The following parameters are set by communication with the application firmware. Please refer to AN288 or

CS4953xx Firmware Users Manual

for more information.

0 < Flash_WEN_CYCLE < 15

0 < Flash_WR_CYCLE < 31

1 < Flash_RD_CYCLE < 31

0 < Flash_OEN_CYCLE < 15

4 < Flash_TURN_CYCLE < 15

ns

EXT_CS# falling to EXT_WE# rising1

ns

EXT_WE# low time

ns

Data Hold after EXT_WE# or EXT_CS# high

0.9 * DCLKP

ns

Address Hold from end of write

0.8 * DCLKP

ns

EXT_WE# falling to data valid

-0

ns

2. A data write transaction is either a burst of two 16-bit half words or four 8-bit bytes with EXT_CS# toggling between

address phases.

TBD

ns

Read Cycle

Single Word Read Cycle1

ns

EXT_CS# falling to EXT_OE# falling1

ns

Data Hold after EXT_OE# or EXT_CS# high

4

ns

Data Input Setup Time

7

ns

Bus Turnaround Cycle Delay, Read to Write Cycle or Static

3. A data read transaction is either a burst of two 16-bit half words (as shown) or four 8-bit bytes with EXT_CS#

remaining asserted between address phases.

ns