Clock Common Mode Voltage − V

50

60

70

80

90

100

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G062

10 MHz

30 MHz

70 MHz

231 MHz

100 MHz

Clock Common Mode Voltage − V

65

67

69

71

73

75

77

79

81

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G063

10 MHz

30 MHz

70 MHz

231 MHz

100 MHz

Clock Duty Cycle − %

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

G064

10 MHz

231 MHz

100 MHz

30 MHz

70 MHz

Clock Input = 3 Vpp

ADS5481

ADS5482, ADS5483

Figure 44. SFDR versus Clock Common Mode

Figure 45. SNR versus Clock Common Mode

Figure 46. SFDR vs Clock Duty Cycle

The ADS5483 is capable of achieving 78.2 dBFS SNR at 100 MHz of analog input frequency. In order to achieve

the SNR at 100 MHz the clock source rms jitter (at the ADC clock input pins) must be at most 205 fsec in order

for the total rms jitter to be 220 fsec due to internal ADC aperture jitter of ~80 fsec. A summary of maximum

recommended rms clock jitter as a function of analog input frequency for the ADS5483 is provided in Table 2.

The equations used to create the table are presented and can be used to estimate required clock jitter for

virtually any pipeline ADC.

Table 2. Recommended Approximate RMS Clock Jitter for ADS5483

ANALOG INPUT FREQUENCY

MEASURED SNR

TOTAL JITTER

MAXIMUM CLOCK JITTER

(MHz)

(dBc)

(fsec rms)

(fsec rms)

1

78.2

19581

19581

10

78

2004

2002

70

77.8

300

289

100

77.2

220

205

130

76

177

158

170

75.8

152

129

230

75.1

122

92

300

73.2

116

84

Copyright © 2008, Texas Instruments Incorporated

Submit Documentation Feedback

23

Product Folder Link(s): ADS5481 ADS5482, ADS5483