AD1883 datasheet(12/20 Pages) AD

12 / 20 page

Rev. 0

Page 12 of 20

April 2008

AD1883

DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS

The digital microphone interface can support one or two digital

microphones using two or three codec pins. Both uniplex (one

microphone per data pin) and multiplex (two microphones

sharing the same data pin) are supported. The timing for these

configurations is shown in Table 6 and Figure 3, Figure 4 and

Figure 5. The interface can generate a microphone clock at

1.5 MHz, 2.0 MHz, or 3.0 MHz to suit quality and power

requirements.

Table 6. Microphone Timing Parameters

Parameter

Description

Min

Typ

Max

Unit

Timing Requirements

DM_CLK (1.5 MHz) Period

Duty Cycle

667

50/50

DM_CLK (2.0 MHz) Period

Duty Cycle

500

50/50

DM_CLK (3.0 MHz) Period

Duty Cycle

333

50/50

DM_CLK Rise Time

DM_CLK Fall Time

5ns

Data Setup to DM_CLK Edge

Data Hold from DM_CLK Edge

Figure 3. Uniplex Microphone Timing

Figure 4. DM_2 Uniplex Microphone Timing

DM_CLK

DM_1/2

DATA VALID

DM_CLK

DM_2

DATA VALID

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