AT89C51IC2-SLSCM datasheet(68/146 Pages) ATMEL

68 / 146 page

AT89C51IC2

4301A–8051–01/04

Table 1. Minimum Reset Capacitor Value for a 50 k

Ω Pull-down Resistor(1)

Note:

These values assume V

DD starts from 0V to the nominal value. If the time between 2

on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully

discharged, leading to a bad reset sequence.

Warm Reset

To achieve a valid reset, the reset signal must be maintained for at least 2 machine

cycles (24 oscillator clock periods) while the oscillator is running. The number of clock

periods is mode independent (X2 or X1).

Watchdog Reset

As detailed in Section “Hardware Watchdog Timer”, page 102, the WDT generates a 96-

clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of

the application in case of external capacitor or power-supply supervisor circuit, a 1 k

Ω

resistor must be added as shown Figure 24.

Figure 24. Reset Circuitry for WDT Reset-out Usage

Oscillator

Start-Up Time

VDD Rise Time

1 ms

10 ms

100 ms

5 ms

820 nF

1.2 µF

12 µF

20 ms

2.7 µF

3.9 µF

12 µF

RST

VSS

To CPU Core

and Peripherals

VDD

From WDT

Reset Source

VSS

VDD

RST

To Other

On-board

Circuitry

AT89C51IC2-SLSCM Datasheet(PDF) 68 Page - ATMEL Corporation

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