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AT89C51IC2-SLSCM Datasheet(PDF) 21 Page - ATMEL Corporation |
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AT89C51IC2-SLSCM Datasheet(HTML) 21 Page - ATMEL Corporation |
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21 / 146 page  21 AT89C51IC2 4301A–8051–01/04 Enhanced Features In comparison to the original 80C52, the AT89C51IC2 implements some new features, which are: • The X2 option • The Dual Data Pointer • The extended RAM • The Programmable Counter Array (PCA) • The Hardware Watchdog • The SPI interface • The 2-wire interface • The 4 level interrupt priority system • The power-off flag • The Power On Reset • The ONCE mode • The ALE disabling • Some enhanced features are also located in the UART and the timer 2 X2 Feature and OSCA Clock Generation The AT89C51IC2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. • Save power consumption while keeping same CPU power (oscillator power saving). • Save power consumption by dividing dynamically the operating frequency by 2 in operating and idle modes. • Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTALA1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. Description The clock for the whole circuit and peripherals is first divided by two before being used by the CPU core and the peripherals. This allows any cyclic ratio to be accepted on XTALA1 input. In X2 mode, as this divider is bypassed, the signals on XTALA1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram.x2 bit is validated on the rising edge of the XTALA1 ÷2 to avoid glitches when switching from X2 to STD mode. Figure 6. shows the switching mode waveforms. Figure 5. Clock Generation Diagram XTALA1 2 CKCON0 X2 8 bit Prescaler F OSCA FXTAL XTALA1:2 F CLK CPU F CLK PERIPH CKSEL CKS F OSCB CKRL 0 1 0 1 |
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