AT89C51IC2-SLSCM datasheet(29/146 Pages) ATMEL

29 / 146 page

AT89C51IC2

4301A–8051–01/04

Table 23. AUXR Register

AUXR - Auxiliary Register (8Eh)

Reset Value = XX0X 00’HSB.XRAM’0b

Not bit addressable

765

43210

XRS1

XRS0

EXTRAM

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

5M0

Pulse length

Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock

periods (default).

Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock

periods.

Reserved

The value read from this bit is indeterminate. Do not set this bit

3XRS1

XRAM Size

XRS1

XRS0

XRAM size

256 bytes (default)

512 bytes

768 bytes

1024 bytes

2XRS0

1EXTRAM

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

(HSB), default setting, XRAM selected.

0AO

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used) (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

AT89C51IC2-SLSCM Datasheet(PDF) 29 Page - ATMEL Corporation

AT89C51IC2-SLSCM Datasheet(HTML) 29 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL