AT89C51IC2-SLSCM datasheet(89/146 Pages) ATMEL

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AT89C51IC2

4301A–8051–01/04

slave address followed by the data direction bit which must be at logic 1 (R) for SSLC to

operate in the slave transmitter mode. After its own slave address and the R bit have

been received, the serial interrupt flag is set and a valid status code can be read from

SSCS. This status code is used to vector to an interrupt service routine. The appropriate

action to be taken for each of these status code is detailed in Table 71. The slave trans-

mitter mode may also be entered if arbitration is lost while SSLC is in the master mode.

If the AA bit is reset during a transfer, SSLC will transmit the last byte of the transfer and

enter state C0h or C8h. SSLC is switched to the not addressed slave mode and will

ignore the master receiver if it continues the transfer. Thus the master receiver receives

all 1’s as serial data. While AA is reset, SSLC does not respond to its own slave

address. However, the 2-wire bus is still monitored and address recognition may be

resume at any time by setting AA. This means that the AA bit may be used to tempo-

rarily isolate SSLC from the 2-wire bus.

Miscellaneous States

There are two SSCS codes that do not correspond to a define SSLC hardware state

(Table 72 ). These codes are discuss hereafter.

Status F8h indicates that no relevant information is available because the serial interrupt

flag is not set yet. This occurs between other states and when SSLC is not involved in a

serial transfer.

Status 00h indicates that a bus error has occurred during an SSLC serial transfer. A bus

error is caused when a START or a STOP condition occurs at an illegal position in the

format frame. Examples of such illegal positions happen during the serial transfer of an

address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To

recover from a bus error, the STO flag must be set and SI must be cleared. This causes

SSLC to enter the not addressed slave mode and to clear the STO flag (no other bits in

SSCON are affected). The SDA and SCL lines are released and no STOP condition is

transmitted.

Notes

SSLC interfaces to the external 2-wire bus via two port pins: SCL (serial clock line) and

SDA (serial data line). To avoid low level asserting on these lines when SSLC is

enabled, the output latches of SDA and SLC must be set to logic 1.

Table 67. Bit frequency configuration

Bit Frequency ( kHz)

CR2

CR1

CR0

FOSCA= 12 MHz

FOSCA = 16 MHz

FOSCA divided by

62.5

256

53.5

71.5

224

62.5

192

100

160

Unused

100

133.3

120

200

266.6

0.5 <. < 62.5

0.67 <. < 83

96 · (256 - reload valueTimer 1)

(reload value range: 0-254 in mode 2)

AT89C51IC2-SLSCM Datasheet(PDF) 89 Page - ATMEL Corporation

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