AT89C51IC2-SLSCM datasheet(86/146 Pages) ATMEL

86 / 146 page

AT89C51IC2

4301A–8051–01/04

Description

The CPU interfaces to the 2-wire logic via the following four 8-bit special function regis-

ters: the Synchronous Serial Control register (SSCON; Table 73), the Synchronous

Serial Data register (SSDAT; Table 74), the Synchronous Serial Control and Status reg-

ister (SSCS; Table 75) and the Synchronous Serial Address register (SSADR Table 78).

SSCON is used to enable SSLC, to program the bit rate (see Table 66), to enable slave

modes, to acknowledge or not a received data, to send a START or a STOP condition

on the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables

SSLC.

In write mode, SSCS is used to select the 2-wire interface and to select the bit rate

source. In read mode, SSCS contains a status code which reflects the status of the 2-

wire logic and the 2-wire bus. The three least significant bits are always zero. The five

most significant bits contains the status code. There are 26 possible status codes. When

SSCS contains F8h, no relevant state information is available and no serial interrupt is

requested. A valid status code is available in SSCS one machine cycle after SI is set by

hardware and is still present one machine cycle after SI has been reset by software.

Table 68.to Table 72. give the status for the master modes and miscellaneous states.

SSDAT contains a byte of serial data to be transmitted or a byte which has just been

received. It is addressable while it is not in process of shifting a byte. This occurs when

2-wire logic is in a defined state and the serial interrupt flag is set. Data in SSDAT

remains stable as long as SI is set. While data is being shifted out, data on the bus is

simultaneously shifted in; SSDAT always contains the last byte present on the bus.

SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which

SSLC will respond when programmed as a slave transmitter or receiver. The LSB is

used to enable general call address (00h) recognition.

Figure 37 shows how a data transfer is accomplished on the 2-wire bus.

Figure 37. Complete data transfer on 2-wire bus

The four operating modes are:

•

Master Transmitter

•

Master Receiver

•

Slave transmitter

•Slave receiver

Data transfer in each mode of operation is shown in Table 68 to Table 72 and Figure 38.

to Figure 41.. These figures contain the following abbreviations:

S : START condition

SDA

SCL

start

condition

MSB

ACK

acknowledgement

signal from receiver

acknowledgement

signal from receiver

3-8

ACK

stop

condition

clock line held low

while interrupts are serviced

AT89C51IC2-SLSCM Datasheet(PDF) 86 Page - ATMEL Corporation

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