33742 datasheet(55/70 Pages) FREESCALE

55 / 70 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 36. LX2HS Control Bits

Logic

Wake-up Inputs Supplied by HS

No.

Yes. Lx inputs sensed at sampling point.

Table 37. HSAUTO Control Bits

Logic

Auto-timing HS in Sleep and Stop modes

OFF.

ON, HS Cyclic, period defined in TIM2 subregister.

Table 38. CAN-INT Control Bits

Logic(66)

Description

Interrupt as soon as CAN bus failure detected.

Interrupt when CAN bus failure detected and fully identified.

Notes

66.

If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by

SPI (refer to CAN Register (CAN) on page 49). After reading the CAN register or setting CAN-INT to logic [1], it will be cleared

automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not

allow clearing the CAN-UF bit.

Table 39. LPC Status Bits

Name

Logic

Failure Description

CANH2VDD

No CANH short to VDD.

CANH short to VDD.

CANH2BAT

No CANH short to VSUP.

CANH short to VSUP.

CANH2GND

No CANH short to GND.

CANH short to GND.

RXPR

No RXD permanent recessive.

RXD permanent recessive.

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