MCF52235 datasheet(41/54 Pages) FREESCALE

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Electrical Characteristics

MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

2.9.1

Equivalent Circuit for ADC Inputs

Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3

is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2,

while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via

S3, with the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The

switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional

capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides

isolation during the charge-sharing phase. One aspect of this circuit is that there is an ongoing input current, which is a function

of the analog input voltage, VREF, and the ADC clock frequency.

fADIC

ADC internal clock

0.1

—

5.0

MHz

RAD

Conversion range

VREFL

—VREFH

tADPU

ADC power-up time5

—6

tAIC cycles

tREC

Recovery from auto standby

—

tAIC cycles

tADC

Conversion time

—

tAIC cycles

tADS

Sample time

—

tAIC cycles

CADI

Input capacitance

—

See Figure 12

—pF

XIN

Input impedance

—

See Figure 12

—W

IADI

Input injection current7, per pin

—

IVREFH

VREFH current

—

VOFFSET

Offset voltage internal reference

—

±11

±15

EGAIN

Gain error (transfer path)

.99

1.01

—

VOFFSET

Offset voltage external reference

—

±3—

SNR

Signal-to-noise ratio

—

62 to 66

—

THD

Total harmonic distortion

—

–75

—

SFDR

Spurious free dynamic range

—

SINAD

Signal-to-noise plus distortion

—

ENOB

Effective number OF bits

9.1

10.6

—

Bits

1 All measurements were made at V

DD = 3.3V, VREFH = 3.3V, and VREFL = ground

2 INL measured from V

IN = VREFL to VIN = VREFH

3 LSB = Least Significant Bit

4 INL measured from V

IN = 0.1VREFH to VIN = 0.9VREFH

5 Includes power-up of ADC and V

REF

6 ADC clock cycles

7 The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the

ADC

Table 35. ADC Parameters1 (continued)

Name

Characteristic

Min

Typical

Max

Unit

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