MCF52235 datasheet(44/54 Pages) FREESCALE

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MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7

Electrical Characteristics

Freescale Semiconductor

2.13

JTAG and Boundary Scan Timing

Figure 14. Test Clock Input Timing

Table 39. JTAG and Boundary Scan Timing

Num

Characteristics1

1 JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.

Symbol

Min

Max

Unit

TCLK frequency of operation

fJCYC

1/4

fsys/2

TCLK cycle period

tJCYC

× t

CYC

—ns

TCLK clock pulse width

tJCW

—

TCLK rise and fall times

tJCRF

Boundary scan input data setup time to TCLK rise

tBSDST

4—

Boundary scan input data hold time after TCLK rise

tBSDHT

—

TCLK low to boundary scan output data valid

tBSDV

033

TCLK low to boundary scan output high Z

tBSDZ

033

TMS, TDI input data setup time to TCLK rise

tTAPBST

4—

J10

TMS, TDI input data hold time after TCLK rise

tTAPBHT

—

J11

TCLK low to TDO data valid

tTDODV

026

J12

TCLK low to TDO high Z

tTDODZ

J13

TRST assert time

tTRSTAT

100

—

J14

TRST setup time (negation) to TCLK high

tTRSTST

—

TCLK

VIL

VIH

(input)

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