7546 datasheet(15/95 Pages) RENESAS

15 / 95 page

Rev.1.21

Nov 15, 2006

page 15 of 93

REJ03B0160-0121

7546 Group

Fig. 13 Memory map of special function register (SFR)

Notes 1: Do not access to the SFR area including nothing.

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Pull-up control register (PULL)

Transmit 1 /Receive 1 buffer register (TB1/RB1)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART1 control register (UART1CON)

Baud rate generator 1 (BRG1)

Port P1P3 control register (P1P3C)

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

Timer count source set register (TCSS)

A/D conversion register (low-order) (ADL)

Prescaler 1 (PRE1)

Timer 1 (T1)

Timer X mode register (TXM)

Prescaler X (PREX)

Timer X (TX)

Serial I/O2 control register (SIO2CON)

UART2 control register (UART2CON)

A/D control register (ADCON)

A/D conversion register (high-order) (ADH)

MISRG

Watchdog timer control register (WDTCON)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt control register 1 (ICON1)

Timer A, B mode register (TABM)

Capture/compare port register (CCPR)

Timer source selection register (TMSR)

Capture mode register (CAPM)

Compare output mode register (CMOM)

Capture/compare status register (CCSR)

Compare interrupt source set register (CISR)

Interrupt request register 2 (IREQ2)

Interrupt control register 2 (ICON2)

On-chip oscillation division ratio selection register (RODR)

Baud rate generator 2 (BRG2)

Timer A (low-order) (TAL)

Timer A (high-order) (TAH)

Timer B (low-order) (TBL)

Timer B (high-order) (TBH)

Transmit 2 / Receive 2 buffer register (TB2/RB2)

Serial I/O2 status register (SIO2STS)

Port P0P3 drive capacity control register (DCCR)

Compare register re-load register (CMPR)

Capture software trigger register (CSTR)

Capture/compare register R/W pointer (CCRP)

Compare register (high-order) (CMPH)

Compare register (low-order) (CMPL)

Capture register 1 (high-order) (CAP1H)

Capture register 1 (low-order) (CAP1L)

Capture register 0 (high-order) (CAP0H)

Capture register 0 (low-order) (CAP0L)

Interrupt source set register (INTSET)

Interrupt source discrimination register (INTDIS)

Reserved

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