7546 datasheet(33/95 Pages) RENESAS

33 / 95 page

Rev.1.21

Nov 15, 2006

page 33 of 93

REJ03B0160-0121

7546 Group

Fig. 32 Structure of timer source selection register

Fig. 33 Structure of compare output mode register

Fig. 34 Structure of capture/compare status register

Fig. 35 Structure of compare interrupt source register

Compare 0 timer source bit

Compare 1 timer source bit

Compare 2 timer source bit

Compare 3 timer source bit

Capture 0 timer source bit

Capture 1 timer source bit

Not used (returns “0” when read)

0: Timer A

1: Timer B

Timer source selection register

(TMSR : address 001F16, initial value: 0016)

Compare 0 output level latch

0: Positive

1: Negative

Compare 1 output level latch

0: Positive

1: Negative

Compare 2 output level latch

0: Positive

1: Negative

Compare 3 output level latch

0: Positive

1: Negative

Compare 0 trigger enable bit

0: Disabled

1: Enabled

Compare 1 trigger enable bit

0: Disabled

1: Enabled

Compare 2 trigger enable bit

0: Disabled

1: Enabled

Compare 3 trigger enable bit

0: Disabled

1: Enabled

Compare output mode register

(CMOM : address 002116, initial value: 0016)

Compare 0 output status bit

0: “L” level output

1: “H” level output

Compare 1 output status bit

0: “L” level output

1: “H” level output

Compare 2 output status bit

0: “L” level output

1: “H” level output

Compare 3 output status bit

0: “L” level output

1: “H” level output

Capture 0 status bit

0: latch 00 captured

1: latch 01 captured

Capture 1 status bit

0: latch 10 captured

1: latch 11 captured

Not used (returns “0” when read)

Capture/Compare status register

(CCSR : address 002216, initial value: 0016)

Compare latch 00 interrupt source bit

Compare latch 01 interrupt source bit

Compare latch 10 interrupt source bit

Compare latch 11 interrupt source bit

Compare latch 20 interrupt source bit

Compare latch 21 interrupt source bit

Compare latch 30 interrupt source bit

Compare latch 31 interrupt source bit

0: Disabled

1: Enabled

Compare interrupt source register

(CISR : address 002316, initial value: 0016)

Fig. 31 Structure of capture/compare port register

Capture 0 input port bits

b1 b0

00: Capture from P00

01: Capture from P10

10: Ring/512

11: Not available

Compare 0 output port bit

0: P01 is I/O port

1: P01 is Compare 0

Compare 1 output port bit

0: P02 is I/O port

1: P02 is Compare 1

Capture 1 input port bit

0: Capture from P30

1: Ring/512

Compare 2 output port bit

0: P31 is I/O port

1: P31 is Compare 2

Compare 3 output port bit

0: P32 is I/O port

1: P32 is Compare 3

Not used (returns “0” when read)

Capture/Compare port register

(CCPR : address 001E16, initial value: 0016)

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